The present invention relates to a semiconductor device including a lead frame, and more particularly relates to a semiconductor device such as an integrated circuit package including an improved lead frame.
A semiconductor device such as an integrated circuit package is manufactured through a series of processing steps such as die bonding or chip bonding, wire bonding and resin molding. The steps are taken on a lead frame punched out of a thin metal plate.
FIG. 1 is a plan view of a conventional lead frame 10. P in FIG. 1 denotes a range corresponding to one integrated circuit package. The lead frame 10 mainly includes an island 40 on which a semiconductor chip is mounted, a plurality of inner lead portions 20 which are indicated by a hatching in FIG. 1 and are connected to the electrodes of the chip mounted on the island, a plurality of outer lead portions 30 which are indicated by another hatching in FIG. 1, continuously extend to the inner lead portions and are connected to a circuit board or the like, and guide rails 50 which have positioning guide holes 55 or the like.
The lead frame 10 is manufactured by punching a thin electroconductive metal plate with dies or by etching. To manufacture the integrated circuit package from the lead frame 10, the semiconductor chip is first bonded to the island 40 of the frame in a chip bonding step. After that, the tips of the inner lead portions 20 of the lead frame 10, which extend toward the island 40, are connected to the electrodes of the chip with gold wires or the like in a wire bonding step. A resin is then molded on the chip on the lead frame 10 in a resin molding step so that the island 40 and the inner lead portions 20 are coated with the resin. The lead frame 10 is thereafter cut off from the guide rails in a lead frame cutoff step so that the integrated circuit package is completed. The lead frame 10 is manufactured for each semiconductor device in conformity with a specification such as the form of a semiconductor chip mounted on the island 40 and the number of the terminals thereof.
Since the lead frame 10 is usually manufactured by punching a flat metal plate or by the like, the frame has a uniform thickness for different portions such as the inner and the outer lead portions 20 and 30. The thickness is generally 0.25 mm for a DIP (Dual In-Line Package), or 0.15 mm for a SOP (Small Outline Package) and a QFP (Quad Flat Package).
The reducibility of the interval between the inner lead portions 20 depends on the thickness of the metal plate, which cannot be set below a limit because each outer lead portion 30 is required to be high enough in mechanical strength. The thickness of the integrated circuit package is determined by the thickness of the lead frame 10, that of the semiconductor chip mounted on the island, the diameter of the bonding wire and so forth.
If the thickness of the lead frame 10 is decreased, the outer lead portions 30 are likely to be made not high enough in mechanical strength and heat conduction capacity. This is a problem. If the thickness of the lead frame 10 is increased, the reduction in the interval between the inner lead portions 20 is likely to be limited to make it impossible to diminish the thickness of the package enough. This is also a problem.